FIG. 1 illustrates a conventional signal transfer circuit 100 of an integrated circuit chip system that is supplied by multiple different power sources. Signal transfer circuitry is configured to transfer digital signals between two different voltage domains, namely source domain 102 that is supplied by vdd_source supply and destination domain 104 that is supplied by vdd_destination supply. In FIG. 1, signal transfer circuit 100 is part of power selection circuitry for the multi-power source system in which the source domain can be running from a selected one of multiple power sources and the destination domain is always running from the power source having the highest voltage, such that vdd_source may be lower than vdd_destination. As shown, a power selection control signal (A) is provided to source domain 102 from power-on-reset circuitry (POR) and power-management-circuitry (PMU) to select one of the multiple system power supplies. Source domain 102 responds to power-selection control-signal A by supplying a source mux-control-signal (C) to destination domain 104, and destination domain 104 responds to logic of destination mux-control-signal (E) to power supply mux circuitry to cause the mux circuitry to select one of multiple alternate power supplies to supply the system circuitry, including POR and PMU circuitries.
As shown in FIG. 1, source domain 102 includes first and second inverters supplied by vdd_source, with the first inverter coupled together to transfer an inverted control signal (B) as shown to the second inverter, which in turn produces the source mux-control-signal C that is supplied to destination domain 104. Destination domain 104 includes an unbalanced level shifter having a ratio of 1 to X in the N-channel metal-oxide-semiconductor (NMOS) field-effect transistor side of the level shifter, and produces the destination mux-control-signal E via an intermediate signal (D) of the level shifter as shown. In particular, FIG. 1 illustrates a startup operating condition for the multi-power source system in which signals A, B and C are supposed to be equal to 0 volts, vdd_source, and 0 volts, respectively (i.e., representing logic states of A=“0”, B=“1”, and C=“0”) so as to control the mux circuitry to select a default startup system power supply corresponding to logic state “0”. However, at system startup, vdd_source can be low and not sufficiently high enough to represent valid logic signals. Under such a condition, the logic values “0” and “1” for signals A, B and C may be misrepresented by hundreds of millivolts instead of the intended values of 0 volts, vdd_source and 0 volts respectively.
Conventional signal transfer circuit 100 is configured to operate assuming that all the logic signals are going to have the same voltage levels, so that signals A, B and C are each going to be in the order of ˜100 mVsh range. Under such conditions, the unbalanced level shifter of destination domain 104 is designed to resolve the destination mux-control-signal E correctly as “0”, even when the source mux-control-signal C input to destination domain 104 is invalid such as during system startup. However, the assumption that the signals in the source domain 102 will always have the same voltage level independent of their logic value is not correct. If voltage of the source mux-control-signal C is higher than inverted control signal B, it can overcome the unbalance in the level shifter and flip the level shifter output to enforce logic of destination mux-control-signal E to be “1”, causing the power supply mux to change the system power supply including the source domain. In such a scenario, the chip might not startup correctly or might never startup at all.